Sr FPGA Engineer - Physical DesignRP1023363Spokane
Life at F5 is never dull. We are constantly identifying industry trends and disruptions, then innovating to get ahead of future customer needs-creating application services that help the world’s leading organizations deliver their critical business apps faster and with the highest levels of flexibility, security, performance, and quality!
But our success isn’t driven solely by what we do. We also care deeply about how we do it. At F5, our culture is how we live, every single day. And it’s producing extraordinary results-not only for our customers, but also for our employees. We understand that your life is about more than just work, so we’re committed to a culture that supports your whole life.
We are looking for an FPGA Physical Design Engineer to join our Spokane product development team. You will be part of a team working with technology vendors and design engineers to solve and optimize a variety of FPGA physical design issues. This position is responsible for assisting other team members in FPGA physical design for Altera and Xilinx FPGAs.
This position determines methods and procedures on new and existing FPGA designs and may provide guidance and mentorship to other engineers. This position works on complex issues where analysis of situations or data requires an in-depth evaluation of a variety of factors.
- Lead FPGA physical design projects for new and existing projects
- Work with Intel Quartus and Xilinx Vivado tools
- Work with Hardware Engineers to develop FPGA pin placement and pin constraints
- Analyze place and route reports
- Develop technical solutions for timing closure issues such as routing congestion, long timing paths, clock rates, etc.
- Work with FPGA Development Engineers to improve design methodologies that help with timing closure
Knowledge, Skills, and Abilities
- Solid understanding of Quartus/Vivado tools
- Experience in high-speed digital design
- Experience with FPGA design flow, including simulation, synthesis, place & route, and timing
- Experience in Verilog /SystemVerilog
- Physical Design experience with understanding of Quartus/Vivado
- Experience in PCIe, 100G I/F Ethernet technologies - an advantage
- Experience with timing constraint definitions. System clocks, false and multicycle timing paths, etc.
- Good communication with teammates
- Bring up an entire P&R environment from scratch to suit design needs
- Enable advanced ground breaking P&R flows and methodologies
- Experience with Intel Stratix 10 and Xilinx UltraScale+ FPGA technologies a plus
- Experience in PCIe, 100G I/F Ethernet technologies a plus
- Perforce knowledge a plus
- BS in Electrical Engineering, Computer Engineering, or related technical field
- 5+ years related work experience
Please note that F5 only contacts candidates through F5 email address (ending with @f5.com) or auto email notification from Yello/Workday (ending with f5.com or @myworkday.com).
Equal Employment Opportunity
It is the policy of F5 to provide equal employment opportunities to all employees and employment applicants without regard to unlawful considerations of race, religion, color, national origin, sex, sexual orientation, gender identity or expression, age, sensory, physical, or mental disability,marital status, veteran or military status, genetic information, or any other classification protected by applicable local, state, or federal laws.This policy applies to all aspects of employment, including, but not limited to, hiring, job assignment, compensation, promotion, benefits, training, discipline, and termination. Reasonable accommodation is available for qualified individuals with disabilities, upon request.